Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology

This paper presents an ultra-low-power subthreshold logic synthesis with bootstrapped sensitive amplifier-Pass transistor logic (B-SAPTL) topology. The design synergizes subthreshold operation's energy efficiency with bootstrapping-enhanced performance and sensitive amplifier-based noise resilience. Our approach overcomes conventional limitations of speed degradation and poor noise margins in subthreshold logic. The proposed synthesis methodology optimizes energy-delay tradeoffs while maintaining variation tolerance. By using B- SAPTL subthreshold logic synthesis, the designed B- SAPTL 16bit adder in 130nm technology achieved 3.59X faster and 66.5% lower energy-delay product than subthreshold standard cell based CLA adder, enabling reliable operation down to 0.2V. These advances make the technique particularly suitable for biomedical implants and IoT edge devices requiring minimum-energy computation. The work provides a systematic framework for synthesizing robust and high-performance subthreshold circuits.