TY - GEN
T1 - Spintronic Memories
T2 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019
AU - Kang, Wang
AU - Zhang, He
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Spintronic memory has been considered as one of the most promising nonvolatile memory candidates to address the leakage power consumption in the post-Moore's era. To date, the spintronic magnetic random access memory (MRAM) family has mainly evolved in four-generation technology advancement, from toggle-MRAM (product in 2006), to STT-MRAM (product in 2012), to SOT-MRAM (intensive RD today), and to VCMA-MRAM (intensive RD today). In addition, another spintronic memory, named racetrack memory (RM), proposed in 2008, has also evolved in two generations from domain wall (DW) based RM to skyrmion-based RM. On the other hand, from the architectural perspective, data transfer bandwidth and the related power consumption has become the most critical bottleneck in vonNeumann computing architecture, owing to the separation of the processor and the memory units and the performance mismatch between the two. Realization of the unity of computing and memory in the same place has opened up a promising research direction of computing-in-memory (CIM). Spintronic memory could be a promising technology to implement the CIM paradigm, owing to its intrinsic processing capability. Lots of interests have been attracted and a number of attempts have been made in this field, within both MRAM and RM. In this paper, we perform a mini review on the RD evolution of spintronic memories: from memory to computing-in-memory. Particularly, we will introduce our recent work on advanced spintronic memories as well as CIM paradigms implemented within spintronic memories.
AB - Spintronic memory has been considered as one of the most promising nonvolatile memory candidates to address the leakage power consumption in the post-Moore's era. To date, the spintronic magnetic random access memory (MRAM) family has mainly evolved in four-generation technology advancement, from toggle-MRAM (product in 2006), to STT-MRAM (product in 2012), to SOT-MRAM (intensive RD today), and to VCMA-MRAM (intensive RD today). In addition, another spintronic memory, named racetrack memory (RM), proposed in 2008, has also evolved in two generations from domain wall (DW) based RM to skyrmion-based RM. On the other hand, from the architectural perspective, data transfer bandwidth and the related power consumption has become the most critical bottleneck in vonNeumann computing architecture, owing to the separation of the processor and the memory units and the performance mismatch between the two. Realization of the unity of computing and memory in the same place has opened up a promising research direction of computing-in-memory (CIM). Spintronic memory could be a promising technology to implement the CIM paradigm, owing to its intrinsic processing capability. Lots of interests have been attracted and a number of attempts have been made in this field, within both MRAM and RM. In this paper, we perform a mini review on the RD evolution of spintronic memories: from memory to computing-in-memory. Particularly, we will introduce our recent work on advanced spintronic memories as well as CIM paradigms implemented within spintronic memories.
KW - MRAM
KW - NAND-SPIN
KW - SOT-MRAM
KW - STT-MRAM
KW - Spintronic memory
KW - VCMA-MRAM
KW - computing in memory
KW - magnetic skyrmion
KW - racetrack memory
UR - https://www.scopus.com/pages/publications/85084956797
U2 - 10.1109/NANOARCH47378.2019.181298
DO - 10.1109/NANOARCH47378.2019.181298
M3 - 会议稿件
AN - SCOPUS:85084956797
T3 - NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
BT - NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 17 July 2019 through 19 July 2019
ER -