@inproceedings{4a89bb4dfb9f4010b10c61a53a291db9,
title = "Software FIFO based interconnection between DSP and FPGA in video encoding system",
abstract = "In video encoding hardware system based on camera link interface, in order to coordinate data transmission between different clock domains, we designed a DSP and FPGA interconnection scheme, in which a software FIFO was used. This article introduced relevant interface interconnects and timing analysis. The system we are using proved the method introduced in the article is stable and efficient to guarantee the speed and correctness of data transmission.",
keywords = "DSP, FIFO, FPGA, Timing control",
author = "Xiaonan Ji and Hongxu Jiang and Chaosheng Xiao and Yuanpeng Wang",
year = "2010",
doi = "10.1109/CISP.2010.5647310",
language = "英语",
isbn = "9781424465149",
series = "Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010",
pages = "3699--3702",
booktitle = "Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010",
note = "2010 3rd International Congress on Image and Signal Processing, CISP 2010 ; Conference date: 16-10-2010 Through 18-10-2010",
}