SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits

As the hardware security gets more and more attentions, Physically Unclonable Function (PUF) has been proposed to provide chip authentication and Intellectual Property protection effectively. The traditional PUF needs long response cycles and independent PUF components, leading to increased power consumption and area overhead. STT-mCell has emerged as a promising spintronic device to be used in logic circuit design with high energy efficiency. However, it is challenging to guarantee the security of the STT-mCell based circuit. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) and exploit the manufacturing process variation (PV) of STTmCell. We introduce a new methodology to select appropriate logic gates in the all-spin chip to generate an identification signature. Finally, a masking scheme is applied for signature improvement. The experimental results show that the uniqueness of the signature is 49.61% and the SD-PUF has area benefits over other designs.