SACIM: A Synapse-inspired Asynchronous CIM with Discharging Feedback, Dynamic Delay and Parallelism Extension for CNN Inference

This brief presents a charge-domain analog compute-in-memory (ACIM) architecture, the Synapse-inspired Asynchronous CIM (SACIM), which addresses key challenges in generality, latency, and parallelism. The architecture includes three structures: a Non-Differential Decoupled (NDDC) bit-cell array for implementing negative signed weights; a Clock-free Asynchronous Controller (CFAC) to dynamically shorten latency; and an asynchronous Pulse-based Analog-to-Digital Converter (PADC) circuit with an NDDC coordination mechanism for parallelism extension. Fabricated in 40nm CMOS, the prototype achieves a peak energy efficiency of 655.78 TOPS/W and a throughput of 1180.4 GOPS, with 5.1 μW static power in a 99,280 μm² area.