Round robin arbiters for virtual channel router

Virtual channel flow control is a well-known technique in design of routers in Networks-on-chip (NoC). This paper analyzes two typical virtual-channel router architectures with different sized switch fabrics. In either of them, the virtual channels do or do not compete for the channels to the switch fabric, and therefore the scheduler performs in an iterative way or not. As the basis of scheduler, the arbiter is impacted by the router architecture and the fashion of scheduling. Two arbiters are proposed for these routers on the basis of PPE, a typical round robin arbiter. The proposed arbiters take above impact into consider, which is ignored in most arbiter designs. They move some process in PPE out of the critical path and perform some crucial process in parallel. The proposed arbiters are implemented in TSMC 0.35μm CMOS technology, and show outstanding improvement in performance by more than 12% or 17% in either scenario. The implementations area of the arbiters is shrunk simultaneity in most cases.