TY - JOUR
T1 - Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology
AU - Cai, Hao
AU - Wang, You
AU - De Barros Naviner, Lirida Alves
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2017/4
Y1 - 2017/4
N2 - In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (Vdd) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome Vdd scaling bottleneck, an efficient framework for Vdd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (Vdd, VBB,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.
AB - In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (Vdd) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome Vdd scaling bottleneck, an efficient framework for Vdd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (Vdd, VBB,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.
KW - FD-SOI
KW - MTJ
KW - Non-volatile logic-in-memory (NV-LIM)
KW - approximate computing
KW - ultra-low power
UR - https://www.scopus.com/pages/publications/84996636597
U2 - 10.1109/TCSI.2016.2621344
DO - 10.1109/TCSI.2016.2621344
M3 - 文章
AN - SCOPUS:84996636597
SN - 1549-8328
VL - 64
SP - 847
EP - 857
JO - IEEE Transactions on Circuits and Systems
JF - IEEE Transactions on Circuits and Systems
IS - 4
M1 - 7748536
ER -