Read disturbance issue and design techniques for nanoscale STT-MRAM

Spin transfer torque magnetic random access memory (STT-MRAM) has been widely considered as one of the most promising candidates for the next-generation nonvolatile memory technologies, thanks to its attractive features, including high density, high speed, low power and high endurance etc. However, our investigation demonstrates that read disturbance may become a significant reliability issue of STT-MRAM. As technology scales down to nanoscale nodes, this read disturbance issue becomes more serious and may turn into be a critical reliability barrier for STT-MRAM commercialization, because the difference between the read and write currents decreases. In this paper, we first give deep analyses on the read disturbance issue of STT-MRAM as technology scales and present a model to capture the features, then we propose a circuit to detect the read disturbance by exploiting its typical features, i.e., (a) the resistance (read current) of the memory cell will have a sudden change if read disturbance occurs; (b) only one-direction of read disturbance can occur during normal read operations. Based on the detection results, further correction technique and optimization strategy are presented to deal with the read disturbance faults as well as to keep the least latency and power overheads.