Quadtree layout

Sourav Bhattacharya; Shekar Kirani; Wei Tek Tsai

Quadtree layout

Sourav Bhattacharya^*
, Shekar Kirani
, Wei Tek Tsai

^*此作品的通讯作者

University of Minnesota Twin Cities

科研成果: 会议稿件 › 论文 › 同行评审

摘要

Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by developing two layout strategies for rectangular grids. Then, two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. We demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.

源语言	英语
页	74-81
页数	8
出版状态	已出版 - 1991
已对外发布	是
活动	Proceedings of the Second Great Lakes Symposium on VLSI - Kalamazoo, MI, USA 期限: 28 2月 1992 → 29 2月 1992

会议

会议	Proceedings of the Second Great Lakes Symposium on VLSI
市	Kalamazoo, MI, USA
时期	28/02/92 → 29/02/92

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引用此

@conference{73215c4fac9a49d89a971ead8c4ec259,

title = "Quadtree layout",

abstract = "Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by developing two layout strategies for rectangular grids. Then, two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. We demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.",

author = "Sourav Bhattacharya and Shekar Kirani and Tsai, \{Wei Tek\}",

year = "1991",

language = "英语",

pages = "74--81",

note = "Proceedings of the Second Great Lakes Symposium on VLSI ; Conference date: 28-02-1992 Through 29-02-1992",

}

TY - CONF

T1 - Quadtree layout

AU - Bhattacharya, Sourav

AU - Kirani, Shekar

AU - Tsai, Wei Tek

PY - 1991

Y1 - 1991

N2 - Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by developing two layout strategies for rectangular grids. Then, two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. We demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.

AB - Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by developing two layout strategies for rectangular grids. Then, two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. We demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.

UR - https://www.scopus.com/pages/publications/0026379353

M3 - 论文

AN - SCOPUS:0026379353

SP - 74

EP - 81

T2 - Proceedings of the Second Great Lakes Symposium on VLSI

Y2 - 28 February 1992 through 29 February 1992

ER -

Quadtree layout

摘要

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引用此