Power optimization in logic synthesis for mixed polarity reed-muller logic circuits

Mixed Polarity Reed-Muller (MPRM) logic draws more and more attention for its advantages over Boolean logic. This paper works on power optimization in logic synthesis for MPRM logic circuits. We present a power estimation model for MPRM logic circuits from a probabilistic point of view. A key feature of this technique is that it provides an accurate and efficient way to handle temporal signal correlations during estimation of average power by using lag-one Markov chains. Besides, an ordered binary decision diagrams-based procedure is used to propagate the temporal correlations from the primary inputs throughout the network. At last, this power estimation model is used in low power synthesis for MPRM logic circuits. This model has been evaluated in C language and a comparative analysis has been presented for many benchmark circuits. The results show that this model gives very good accuracy and does well in low power design for MPRM logic circuit.