Performance analysis of a digital capacitance measuring circuit

This paper presents the design and study of a digital capacitance measuring circuit with theoretical analysis, numerical simulation, and experimental evaluation. The static and dynamic performances of the capacitance measuring circuit are first defined, including signal-to-noise ratio (SNR), standard deviation, accuracy, linearity, sensitivity, and response time, within a given measurement range. Then numerical simulation is carried out to analyze the SNR and standard deviation of the circuit, followed by experiments to validate the overall performance of the circuit. The simulation results show that when the standard deviation of noise is 0.08 mV and the measured capacitance decreases from 6 pF to 3 fF, the SNR decreases from 90 dB to 22 dB and the standard deviation is between 0.17 fF and 0.24 fF. The experimental results show that when the measured capacitance decreases from 6 pF to 40 fF and the data sampled in a single period are used for demodulation, the SNR decreases from 88 dB to 40 dB and the standard deviation is between 0.18 fF and 0.25 fF. The maximum absolute error and relative error are 5.12 fF and 1.26%, respectively. The SNR and standard deviation can be further improved if the data sampled in more than one period are used for demodulation by the circuit.