Partly-parallel coder structure of quasi-cyclic low-density parity-check codes

To meet the requirement of using multi-rate low-density parity-check (LDPC) codes in a communication system, a multi-rate quasi-cyclic LDPC (QC-LDPC) codes coder architecture is presented and implemented on an Altera field programmable gate array (FPGA) device. The coder is divided according to the function into four major parts: the input storage unit (ISU), the generator matrix storage unit (GMSU), the matrix multiplying unit (MMU), and the output storage unit (OSU). Combining several small memories instead of a single large one to keep the input information bits can minimize the null storage space of the ISU. Every vector of the multi-rate generator matrixes is reserved in the memories based on the generator matrix characteristic in the GMSU. The MMU performs matrix multiplication with the information bits, and is made up of a shift register, a register, some AND doors and some XOR doors in the circuit. The number of the MMU is equal to that of the GMSU. The OSU includes two memories, organized in ping-pang format, so as to improve the coding rate. Using pin selection, three operating modes, i.e., the 0.4, 0.6. and 0.8 code modes, are supported. Synthesized using FPGA EP1S801508C7, the result indicates that the proposed multi-rate LDPC code coder uses only 5339 logic elements, or 7% of the total, and 439296 memory bits, or 6% of the total.