Partially parallel decoder structure of multi-rate RS codes

To meet the requirement of using multi-rate RS(Reed-Solomon) codes in the communication system, a multi-rate partially parallel RS codes decoder architecture was presented. This decoder can be divided into three major blocks by its function: the syndrome computation block, the key-equation solver block and the Chien search and error evaluator block. According to the characteristic of the two RS codes specified in CCSDS standards, the syndrome computation cells of different code rates which have the same factor share the same hardware resources. A novel partial parallel architecture was used in solving the key-equation, which makes multiplexed units and non-multiplexed units operate concurrently, so as to reduce the waiting time in computation as well as improve decoding efficiency. In Chien search and error evaluator block, look-up tables were used to realize the multiply operation in Forney algorithm. Besides, multiplexed structures were used in inverse operation cells and Chien search cells in order to reduce the hardware resources. Using pin selection, two decoding modes, namely, RS(255, 223) and RS(255, 239) were supported. The synthesis result which is implemented in Altera's FPGA devices indicates that the proposed multi-rate RS code decoder using 2981 logic elements and 9472 memory bits.