Parallel voting RANSAC and its implementation on FPGA

Random Sample Consensus (RANSAC) performs poor with the mass of data, high outliers ratio and complicated models. In this paper, a highly parallel voting version of RANSAC is presented. On the basis of parallelizing the hypothetical stage and generating multiple models simultaneously, a novel strategy of voting to determine whether a point belongs to inliers is proposed. Conventional search for the inliers relative to the best model is saved. On parallel platforms represented by FPGA, this algorithm can take advantage of the parallel architecture and characteristics to achieve deep-pipelined parallel computing. Experiments demonstrate the good robustness of the proposed algorithm and its considerable improvement of both speed and throughput.