TY - GEN
T1 - Parallel implementation of high resolution radar signal processing system based On multi-IC architecture
AU - Hong, Xiang
AU - Jun, Wang
AU - Yuxi, Zhang
PY - 2013
Y1 - 2013
N2 - In this paper, a pulsed doppler (PD) radar signal processing algorithm designed to track targets with high velocity is implemented in hardware based on 4 ADSP-TS201 TigerSHARC processors and 4 XC4VSX55. Both the radar signal processing algorithm and hardware architecture are proposed. To map the algorithm effectively, pipeline optimization on system and instruction levels are adopted, and various factors are taken into consideration, such as system complexity, balance of the task in each processor, communication between processors. Practical experiment proves that both the design of this hardware platform and the realization of algorithm are effective, real-time and reliable.
AB - In this paper, a pulsed doppler (PD) radar signal processing algorithm designed to track targets with high velocity is implemented in hardware based on 4 ADSP-TS201 TigerSHARC processors and 4 XC4VSX55. Both the radar signal processing algorithm and hardware architecture are proposed. To map the algorithm effectively, pipeline optimization on system and instruction levels are adopted, and various factors are taken into consideration, such as system complexity, balance of the task in each processor, communication between processors. Practical experiment proves that both the design of this hardware platform and the realization of algorithm are effective, real-time and reliable.
KW - DSP+FPGA
KW - PD radar
KW - Parallel processing algorithm
KW - Pipeline optimization
UR - https://www.scopus.com/pages/publications/84894537582
U2 - 10.1049/cp.2013.0296
DO - 10.1049/cp.2013.0296
M3 - 会议稿件
AN - SCOPUS:84894537582
SN - 9781849196031
T3 - IET Conference Publications
BT - IET International Radar Conference 2013
T2 - IET International Radar Conference 2013
Y2 - 14 April 2013 through 16 April 2013
ER -