Optimized LRU Algorithm for STT-MRAM/SRAM Hybrid Cache Architecture

The rapid development of Non-Volatile Memory (NVM) prompts advanced computer architecture. With byte addressing method, low static power consumption and non-volatility, spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as one of the most promising alternatives to SRAM for cache application. However, STT-MRAM has three times the read latency compared to SRAM. In addition, the simple replacement scheme cannot tap into the advantages of NVM. In this article, we propose a hybrid cache architecture integrating both SRAM and STT-MRAM. In this hybrid cache architecture, STT-MRAM acts as the backup of SRAM. The system queries the counter and valid bits of the cache line through byte addressing, and forms a dynamic matrix of the cache lines that meet the conditions. The least-recently-used (LRU) algorithm confirms the starting node of the cache line in the dynamic matrix according to the capacity of the cache each time, and then searches for the cache line that needs the cache capacity according to the starting node to perform data replacement. The simulation results demonstrate that the system access time can be reduced by 1.2 times compared with previous LRU.