TY - GEN
T1 - Nonvolatile radiation hardened DICE latch
AU - Pang, Tingting
AU - Kang, Wang
AU - Ran, Yi
AU - Zhang, Youguang
AU - Lv, Weifeng
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/4/20
Y1 - 2016/4/20
N2 - Spintronic-based integrated circuits have been widely considered as potential candidates for space application, due to the fact that their core devices (e.g. magnetic tunnel junction, MTJ) are intrinsic insensitive to radiation effects. However, their CMOS peripheral circuits are still vulnerable to radiation effects. In order to solve this problem, radiation hardening techniques (by process or by design) are supposed to be developed. Hardening by process turns to be impractical, as it is relatively expensive and inefficient, whereas solutions by design at circuit level are currently preferred. Specifically, the dual interlocked storage cell (DICE) has been proposed for radiation hardening design. The DICE is relatively robust against single event upset (SEU), but it is power-inefficiency as it uses a dual structure to store only one bit of data. In addition, the DICE should be always power-on to retain data, consuming much static power. In this paper, we propose a nonvolatile DICE latch (NV-DICE), by integrating two magnetic tunnel junctions (MTJs) into the cell, which exhibits great potential for protecting against SEU with nonvolatility for low power consumption. By utilizing STMicroelectronics 40 nm design kit and a compact MTJ model, hybrid simulations are performed to demonstrate the functionality and performance of the proposed NV-DICE.
AB - Spintronic-based integrated circuits have been widely considered as potential candidates for space application, due to the fact that their core devices (e.g. magnetic tunnel junction, MTJ) are intrinsic insensitive to radiation effects. However, their CMOS peripheral circuits are still vulnerable to radiation effects. In order to solve this problem, radiation hardening techniques (by process or by design) are supposed to be developed. Hardening by process turns to be impractical, as it is relatively expensive and inefficient, whereas solutions by design at circuit level are currently preferred. Specifically, the dual interlocked storage cell (DICE) has been proposed for radiation hardening design. The DICE is relatively robust against single event upset (SEU), but it is power-inefficiency as it uses a dual structure to store only one bit of data. In addition, the DICE should be always power-on to retain data, consuming much static power. In this paper, we propose a nonvolatile DICE latch (NV-DICE), by integrating two magnetic tunnel junctions (MTJs) into the cell, which exhibits great potential for protecting against SEU with nonvolatility for low power consumption. By utilizing STMicroelectronics 40 nm design kit and a compact MTJ model, hybrid simulations are performed to demonstrate the functionality and performance of the proposed NV-DICE.
KW - Dual interlocked storage cell (DICE)
KW - nonvolatility
KW - radiation hardened design
KW - single event upset (SEU)
UR - https://www.scopus.com/pages/publications/84978136447
U2 - 10.1109/NVMTS.2015.7457431
DO - 10.1109/NVMTS.2015.7457431
M3 - 会议稿件
AN - SCOPUS:84978136447
T3 - 2015 15th Non-Volatile Memory Technology Symposium, NVMTS 2015
BT - 2015 15th Non-Volatile Memory Technology Symposium, NVMTS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th Non-Volatile Memory Technology Symposium, NVMTS 2015
Y2 - 12 October 2015 through 14 October 2015
ER -