TY - JOUR
T1 - Nonvolatile boolean logic block based on ferroelectric tunnel memristor
AU - Wang, Zhaohao
AU - Zhao, Weisheng
AU - Kang, Wang
AU - Zhang, Yue
AU - Klein, Jacques Olivier
AU - Ravelosona, Dafiné
AU - Zhang, Youguang
AU - Chappert, Claude
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/11/1
Y1 - 2014/11/1
N2 - Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work.
AB - Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work.
KW - Detection window
KW - ferroelectric domain
KW - ferroelectric tunnel memristor (FTM)
KW - nonvolatile (NV) Boolean logic
UR - https://www.scopus.com/pages/publications/84915748451
U2 - 10.1109/TMAG.2014.2329774
DO - 10.1109/TMAG.2014.2329774
M3 - 文章
AN - SCOPUS:84915748451
SN - 0018-9464
VL - 50
JO - IEEE Transactions on Magnetics
JF - IEEE Transactions on Magnetics
IS - 11
M1 - 6971560
ER -