Modeling TTEthernet Startup Service in SystemC for Verifying Fault-Tolerant Protocol under Fail-Omission Scenarios

Distributed clock synchronization protocol, adopted by TTEthernet, must be analyzed in a comprehensive manner, especially in failure mode or failure pressure to meet the requirements of safety critical certification. Although codes of the functional layer of the hardware description model cannot be integrated, they can gradually refine the highly abstract model into a behavior level model or register level model with using SystemC class library. Because fail-omission failure may occur in each state of the synchronization devices, SystemC is used to establish the executable model of synchronization master and compression master, and then to build the corresponding testbench, which can show the working state of startup scenario featuring a faulty synchronization master. This method not only tests the consistency of hardware implementation and agreement but also verifies the correctness of the fault-tolerant protocol under failure pressure. This process provides a rapid prototyping basis for the development of field programmable devices from requirements definition to hardware implementation, improves design efficiency and saves design costs especially for multiple embedded designs with time-based real-time network.