Matrix Inversion Acceleration Using SOT-MRAM-Based Analog Matrix Computation Architecture

Matrix inversion imposes a considerable computational burden in modern communication systems. Computing-in-memory (CIM) architectures provide a promising solution by minimizing data movement and Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM) is particularly promising due to its excellent endurance, making it suitable for communication tasks involving frequent data refresh operations. However, SOT-MRAM is limited in computational precision due to inherent device stochasticity and its single-bit storage characteristic. To address this challenge, we present an analog matrix computation (AMC) architecture employing SOT-MRAM and zero-offset weight mapping technique for matrix inversion computing in a 55nm CMOS process. The results demonstrate an 11.45× energy reduction for the fourth-order case compared to traditional Von Neumann architectures and a progressively greater delay reduction with increasing order.