Low Store Power High-Speed High-Density Nonvolatile SRAM Design With Spin Hall Effect-Driven Magnetic Tunnel Junctions

As static power caused by leakage currents has become a critical challenge for the CMOS technology power-gating techniques, which employ nonvolatile data retention circuits, e.g., nonvolatile static random-access memory (NV-SRAM) are expected to efficiently solve this challenge. One of the key features of NV-SRAM is to utilize nonvolatile devices, such as resistive RAM, phase change memory, and magnetic tunnel junction (MTJ), to store the runtime data when system is in the standby power-off state. Among them, MTJ-based NV-SRAM is widely considered as the most potential candidate in high-speed, low-power, and high-reliability applications, thanks to the advantageous features of the MTJ devices, such as fast data store/restore operation, low critical writing current density, and high endurance. In this paper, we propose a novel NV-SRAM design with spin Hall effect (SHE)-driven MTJ devices. In specific, two embodiments are designed based on the magnetic anisotropy property (i.e., in-plane or perpendicular) of the MTJ device. Using our previously developed SHE-MTJ model and a CMOS design kit, circuit operation and performance of the proposed NV-SRAM designs were demonstrated at the 40-nm technology node. Simulation results show that our proposed NV-SRAM design achieves performance improvement in terms of power, delay, and area, compared with conventional designs.