TY - GEN
T1 - Low power wireless receiver in CMOS mixed-signal for bio-telemetry implantable system
AU - Li, Hongge
AU - Zhang, Youguang
PY - 2008
Y1 - 2008
N2 - A novel mixed-signal interface is presented for implantable interface receiver consists of an analog front-end and a digital processing circuit. The analog circuit consists of mainly an amplifier, an ASK demodulator, a clock extraction and a power recovery. In this paper, the amplifier and the ASK demodulator are described and provided without the capacitor and the resistor, fully integrated, low-power circuit. We also developed the processing circuit with the digital technology, so that implementing the correct synchronous signal. The carrier frequency of the circuit is applied in the 10MHz range, the data rates up to 1M bit/s are supported, suitable for complex implantable microsystem such as the brain neural mutual interface and so on. Low-power and high-performance implantable interface using a CMOS technology has been designed, fabricated and verified. All of circuits were implemented in a standard 0.18-μm CMOS technology. The power dissipation of the mixed-signal microsystem is verified to be less than 2.75mW @ 1.8V.
AB - A novel mixed-signal interface is presented for implantable interface receiver consists of an analog front-end and a digital processing circuit. The analog circuit consists of mainly an amplifier, an ASK demodulator, a clock extraction and a power recovery. In this paper, the amplifier and the ASK demodulator are described and provided without the capacitor and the resistor, fully integrated, low-power circuit. We also developed the processing circuit with the digital technology, so that implementing the correct synchronous signal. The carrier frequency of the circuit is applied in the 10MHz range, the data rates up to 1M bit/s are supported, suitable for complex implantable microsystem such as the brain neural mutual interface and so on. Low-power and high-performance implantable interface using a CMOS technology has been designed, fabricated and verified. All of circuits were implemented in a standard 0.18-μm CMOS technology. The power dissipation of the mixed-signal microsystem is verified to be less than 2.75mW @ 1.8V.
UR - https://www.scopus.com/pages/publications/63249091122
U2 - 10.1109/EDSSC.2008.4760665
DO - 10.1109/EDSSC.2008.4760665
M3 - 会议稿件
AN - SCOPUS:63249091122
SN - 9781424425402
T3 - 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
BT - 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
T2 - 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
Y2 - 8 December 2008 through 10 December 2008
ER -