Low-Inductance Optimization of EasyPACK 1B Six-Pack SiC Power Module

Silicon carbide (SiC) MOSFETs enable high-switching speed and superior thermal conductivity in high-power-density applications. However, their performance is often constrained by packaging parasitic inductance, which aggravates turn-off voltage overshoot and electromagnetic interference (EMI). Although various advanced packaging techniques have been developed, they often face challenges in ensuring compatibility with existing industrial manufacturing processes. A comprehensive approach to inductance minimization in the EasyPACK 1Bsix-pack SiC power module is proposed, combining the optimization of power loop layout with integrated decoupling capacitors. The proposed solution retains the original housing and mechanical structure, ensuring compatibility with conventional manufacturing processes while achieving enhanced electrical performance. The fabricated modules have been experimentally validated using double-pulse test under 400 V/40 A, demonstrating a parasitic inductance of approximately 6.2 nH, representing a 70% reduction compared to the commercial module. The results also show that the proposed module achieves a 67% reduction in turn-off voltage overshoot.