JPEG image decoding and display system design based on ZedBoard development platform

JPEG decoding algorithm has become an international mainstream image compression standard, because of its wide range of applications, easy implementation, supporting for lossless compression and other characteristics[1]. This thesis is to explain how to design a high-resolution JPEG image decoding system architecture, which supports for real-time display and has good scalability as well. We choosing newly developed ZedBoard development board of Xilinx corporation as development platform and EDK (Embedded Development Kit) as development environment[2]. The design flow is to read JPEG stream data stored in DDR and store the decoding data in DDR after finishing the hardware decoding. Finally we use VDMA to translate the stream in order to display on a monitor connected to the HDMI interface. In this system, we adopt AXI bus with a hierarchical technology to achieve IP interconnection, adopt hardware decoding to achieve high-resolution image decoding and adopt VDMA hardware data movement to achieve real-time display based on ARM Cortex A9 dual-core processor software design.