Janus: An FPGA-based system for high-performance scientific computing

Francesco Belletti; Marco Guidetti; Andrea Maiorano; Filippo Mantovani; Sebastiano Fabio Schifano; Raffaele Tripiccione; Maria Cotallo; Sergio Perez-Gaviro; Daniele Sciretti; Jos Luis Velasco; Andrs Cruz; Denis Navarro; Alfonso Tarancon; Luis Antonio Fernandez; Victor Martin-Mayor; Antonio Muñoz-Sudupe; David Yllanes; Antonio Gordillo-Guerrero; Juan Jess Ruiz-Lorenzo; Enzo Marinari; Giorgio Parisi; Mauro Rossi; Gianpaolo Zanier

doi:10.1109/MCSE.2009.11

Janus: An FPGA-based system for high-performance scientific computing

Francesco Belletti^*
, Marco Guidetti
, Andrea Maiorano
, Filippo Mantovani
, Sebastiano Fabio Schifano
, Raffaele Tripiccione
, Maria Cotallo
, Sergio Perez-Gaviro
, Daniele Sciretti
, Jos Luis Velasco
, Andrs Cruz
, Denis Navarro
, Alfonso Tarancon
, Luis Antonio Fernandez
, Victor Martin-Mayor
, Antonio Muñoz-Sudupe
, David Yllanes
, Antonio Gordillo-Guerrero
, Juan Jess Ruiz-Lorenzo
, Enzo Marinari

Giorgio Parisi, Mauro Rossi, Gianpaolo Zanier

^*此作品的通讯作者

University of Ferrara
Institute of Biocomputation and Physics of Complex Systems
University of Zaragoza
Complutense University
University of Extremadura
University of Rome La Sapienza
ETHlab

科研成果: 期刊稿件 › 文章 › 同行评审

77 引用（Scopus）

摘要

Janus is a reconfigurable field-programmable gate arrays (FPGAs)-based computing system that can be used for scientific computing. A Janus processor has the capability to perform the 10¹³ Monte Carlo steps on one system. Janus is a reconfigurable architecture that can be used to configure a high-performance application. Janus architecture is based on the modules having a computational core connected to a host system of a networked PCs. The Janus core also has 4 × 4 arrays of FPGA-based processing elements with nearest-neighbor data links. The Janus core is based on a 4 × 4 2D grid of processing elements with nearest-neighbor links in both directions. Janus application development process includes designing firmware to configure the simulation processors (SPs) and developing the related host-based software.

源语言	英语
期刊论文编号	4720223
页（从-至）	48-58
页数	11
期刊	Computing in Science and Engineering
卷	11
期	1
DOI	https://doi.org/10.1109/MCSE.2009.11
出版状态	已出版 - 2009
已对外发布	是

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10.1109/MCSE.2009.11

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Belletti, F., Guidetti, M., Maiorano, A., Mantovani, F., Schifano, S. F., Tripiccione, R., Cotallo, M., Perez-Gaviro, S., Sciretti, D., Velasco, J. L., Cruz, A., Navarro, D., Tarancon, A., Fernandez, L. A., Martin-Mayor, V., Muñoz-Sudupe, A., Yllanes, D., Gordillo-Guerrero, A., Ruiz-Lorenzo, J. J., ... Zanier, G. (2009). Janus: An FPGA-based system for high-performance scientific computing. Computing in Science and Engineering, 11(1), 48-58. 期刊论文 4720223. https://doi.org/10.1109/MCSE.2009.11

@article{ed226d9b0fe14ad0827c1f88650dd388,

title = "Janus: An FPGA-based system for high-performance scientific computing",

abstract = "Janus is a reconfigurable field-programmable gate arrays (FPGAs)-based computing system that can be used for scientific computing. A Janus processor has the capability to perform the 1013 Monte Carlo steps on one system. Janus is a reconfigurable architecture that can be used to configure a high-performance application. Janus architecture is based on the modules having a computational core connected to a host system of a networked PCs. The Janus core also has 4 {\texttimes} 4 arrays of FPGA-based processing elements with nearest-neighbor data links. The Janus core is based on a 4 {\texttimes} 4 2D grid of processing elements with nearest-neighbor links in both directions. Janus application development process includes designing firmware to configure the simulation processors (SPs) and developing the related host-based software.",

author = "Francesco Belletti and Marco Guidetti and Andrea Maiorano and Filippo Mantovani and Schifano, \{Sebastiano Fabio\} and Raffaele Tripiccione and Maria Cotallo and Sergio Perez-Gaviro and Daniele Sciretti and Velasco, \{Jos Luis\} and Andrs Cruz and Denis Navarro and Alfonso Tarancon and Fernandez, \{Luis Antonio\} and Victor Martin-Mayor and Antonio Mu{\~n}oz-Sudupe and David Yllanes and Antonio Gordillo-Guerrero and Ruiz-Lorenzo, \{Juan Jess\} and Enzo Marinari and Giorgio Parisi and Mauro Rossi and Gianpaolo Zanier",

year = "2009",

doi = "10.1109/MCSE.2009.11",

language = "英语",

volume = "11",

pages = "48--58",

journal = "Computing in Science and Engineering",

issn = "1521-9615",

publisher = "IEEE Computer Society",

number = "1",

}

Belletti, F, Guidetti, M, Maiorano, A, Mantovani, F, Schifano, SF, Tripiccione, R, Cotallo, M, Perez-Gaviro, S, Sciretti, D, Velasco, JL, Cruz, A, Navarro, D, Tarancon, A, Fernandez, LA, Martin-Mayor, V, Muñoz-Sudupe, A, Yllanes, D, Gordillo-Guerrero, A, Ruiz-Lorenzo, JJ, Marinari, E, Parisi, G, Rossi, M & Zanier, G 2009, 'Janus: An FPGA-based system for high-performance scientific computing', Computing in Science and Engineering, 卷 11, 号码 1, 4720223, 页码 48-58. https://doi.org/10.1109/MCSE.2009.11

TY - JOUR

T1 - Janus

T2 - An FPGA-based system for high-performance scientific computing

AU - Belletti, Francesco

AU - Guidetti, Marco

AU - Maiorano, Andrea

AU - Mantovani, Filippo

AU - Schifano, Sebastiano Fabio

AU - Tripiccione, Raffaele

AU - Cotallo, Maria

AU - Perez-Gaviro, Sergio

AU - Sciretti, Daniele

AU - Velasco, Jos Luis

AU - Cruz, Andrs

AU - Navarro, Denis

AU - Tarancon, Alfonso

AU - Fernandez, Luis Antonio

AU - Martin-Mayor, Victor

AU - Muñoz-Sudupe, Antonio

AU - Yllanes, David

AU - Gordillo-Guerrero, Antonio

AU - Ruiz-Lorenzo, Juan Jess

AU - Marinari, Enzo

AU - Parisi, Giorgio

AU - Rossi, Mauro

AU - Zanier, Gianpaolo

PY - 2009

Y1 - 2009

N2 - Janus is a reconfigurable field-programmable gate arrays (FPGAs)-based computing system that can be used for scientific computing. A Janus processor has the capability to perform the 1013 Monte Carlo steps on one system. Janus is a reconfigurable architecture that can be used to configure a high-performance application. Janus architecture is based on the modules having a computational core connected to a host system of a networked PCs. The Janus core also has 4 × 4 arrays of FPGA-based processing elements with nearest-neighbor data links. The Janus core is based on a 4 × 4 2D grid of processing elements with nearest-neighbor links in both directions. Janus application development process includes designing firmware to configure the simulation processors (SPs) and developing the related host-based software.

AB - Janus is a reconfigurable field-programmable gate arrays (FPGAs)-based computing system that can be used for scientific computing. A Janus processor has the capability to perform the 1013 Monte Carlo steps on one system. Janus is a reconfigurable architecture that can be used to configure a high-performance application. Janus architecture is based on the modules having a computational core connected to a host system of a networked PCs. The Janus core also has 4 × 4 arrays of FPGA-based processing elements with nearest-neighbor data links. The Janus core is based on a 4 × 4 2D grid of processing elements with nearest-neighbor links in both directions. Janus application development process includes designing firmware to configure the simulation processors (SPs) and developing the related host-based software.

UR - https://www.scopus.com/pages/publications/58149138784

U2 - 10.1109/MCSE.2009.11

DO - 10.1109/MCSE.2009.11

M3 - 文章

AN - SCOPUS:58149138784

SN - 1521-9615

VL - 11

SP - 48

EP - 58

JO - Computing in Science and Engineering

JF - Computing in Science and Engineering

IS - 1

M1 - 4720223

ER -

Janus: An FPGA-based system for high-performance scientific computing

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