Investigation of Magnetic Immunity of SOT-MRAM with Shielding Package

Benefiting from high speed, high endurance, and low power consumption, SOT-MRAM holds broad application prospects in fields such as intelligent computing, aerospace, and industrial manufacturing. However, its sensitivity to external magnetic fields remains a major challenge to its reliability. This paper investigates the failure behavior of SOT-MRAM under external magnetic fields by introducing an asymmetric dual-layer magnetic shielding structure within the package (a bottom Permalloy shielding pad matching the chip size and a smaller one on the top). This study systematically evaluates the impact of shielding effectiveness on various factors, including the direction of the magnetic field, shielding layers' thickness, offset, distance, and bending. Furthermore, under strong magnetic fields, a strip-shaped failure pattern perpendicular to the magnetic field direction emerged in the central region of the chip. This results from preferential magnetic saturation in the center of the bottom shield, creating a localized leakage magnetic flux path between the upper and lower shields. This work provides optimization directions for SOT-MRAM packaging design.