TY - GEN
T1 - InfiNAS
T2 - 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
AU - Chen, Jiayu
AU - Li, Maoliang
AU - Zheng, Zihao
AU - Liu, Chenchen
AU - Zhao, Weisheng
AU - Chen, Xiang
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - As AI enters the era of large foundation models, neural network architecture design remains a critical research focus. Recent studies emphasize high-order computation and infinite-dimensional feature interactions, introducing new computation-memory patterns and challenges for neural architecture search (NAS). In this work, we analyze the search space of high-order neural networks under infinite-dimensional design, investigating how scaling factors such as width, depth, rank, and order affect performance and efficiency. We then propose InfiNAS, a NAS framework that automatically discovers effective high-order architectures. Experiments demonstrate that InfiNAS achieves superior accuracy and the best computation-memory trade-off compared to state-of-the-art networks, reducing memory access by up to 69% while maintaining high performance.
AB - As AI enters the era of large foundation models, neural network architecture design remains a critical research focus. Recent studies emphasize high-order computation and infinite-dimensional feature interactions, introducing new computation-memory patterns and challenges for neural architecture search (NAS). In this work, we analyze the search space of high-order neural networks under infinite-dimensional design, investigating how scaling factors such as width, depth, rank, and order affect performance and efficiency. We then propose InfiNAS, a NAS framework that automatically discovers effective high-order architectures. Experiments demonstrate that InfiNAS achieves superior accuracy and the best computation-memory trade-off compared to state-of-the-art networks, reducing memory access by up to 69% while maintaining high performance.
KW - Infinite-Dimensional Neural Networks
KW - Neural Architecture Search
KW - Parameter Scaling
UR - https://www.scopus.com/pages/publications/105043519729
U2 - 10.1109/ISCAS66217.2026.11562843
DO - 10.1109/ISCAS66217.2026.11562843
M3 - 会议稿件
AN - SCOPUS:105043519729
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 229
EP - 233
BT - ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 24 May 2026 through 27 May 2026
ER -