TY - JOUR
T1 - In-Memory Logic Operation Based on a Novel Spin-Orbit Torque MRAM
AU - Wang, Chenyi
AU - Wang, Min
AU - Chen, Zanhong
AU - Yan, Zhengjie
AU - Xu, Xiaoyang
AU - Bai, Yue
AU - Zhang, Hongchao
AU - Shi, Kewen
AU - Wang, Zhaohao
N1 - Publisher Copyright:
© 1980-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - Spin-orbit torque (SOT)-based in-memory logic designs offer a promising approach to alleviating the memory wall problem. However, in existing schemes, the basic cells mainly rely on auxiliary physical mechanisms or transistors, which considerably limit their applicability. In this work, we demonstrate a novel SOT-based device fabricated on an 8-inch wafer platform, featuring dual canted magnetic tunnel junctions (MTJs) monolithically integrated via a well-designed SOT channel. This device breakthrough simultaneously achieves fast switching (current density is 19.8 MA/cm2@5 ns), multi-bit storage, and in-memory logic operations via SOT alone, while maintaining compatibility with CMOS technology ( σ % under 7.25% in arrays). By exploiting synergistic voltage control, we achieve in situ XOR operation and edge detection with error tolerance and competitive F-measure. Our proposed scheme provides a potential pathway toward next-generation large-scale, ultra-fast, and energy-efficient in-memory logic.
AB - Spin-orbit torque (SOT)-based in-memory logic designs offer a promising approach to alleviating the memory wall problem. However, in existing schemes, the basic cells mainly rely on auxiliary physical mechanisms or transistors, which considerably limit their applicability. In this work, we demonstrate a novel SOT-based device fabricated on an 8-inch wafer platform, featuring dual canted magnetic tunnel junctions (MTJs) monolithically integrated via a well-designed SOT channel. This device breakthrough simultaneously achieves fast switching (current density is 19.8 MA/cm2@5 ns), multi-bit storage, and in-memory logic operations via SOT alone, while maintaining compatibility with CMOS technology ( σ % under 7.25% in arrays). By exploiting synergistic voltage control, we achieve in situ XOR operation and edge detection with error tolerance and competitive F-measure. Our proposed scheme provides a potential pathway toward next-generation large-scale, ultra-fast, and energy-efficient in-memory logic.
KW - Spin-orbit torque
KW - dual canted magnetic tunnel junctions
KW - in-memory logic
UR - https://www.scopus.com/pages/publications/105015404606
U2 - 10.1109/LED.2025.3607381
DO - 10.1109/LED.2025.3607381
M3 - 文章
AN - SCOPUS:105015404606
SN - 0741-3106
VL - 46
SP - 2208
EP - 2211
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 11
ER -