TY - GEN
T1 - Improving parallel modularization algorithm of large complex fault trees
AU - Li, Zhifeng
AU - Ren, Yi
AU - Liu, Linlin
AU - Wang, Zili
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/4/5
Y1 - 2016/4/5
N2 - Modularization is a significant way to ease the challenge of evaluating large-scale fault trees known as a NP-hard problem, especially for BDD algorithm. In our previous work, we proposed an effective parallel modularization algorithm for large-scale coherent fault trees which only include gates with AND logic and OR logic. But in real engineering scenarios, fault trees usually consist of many complex static logic gates (i.e. K out of N gate, NOT gate, etc.) and dynamic logic gates (i.e. sequence gate, functional dependency gate, etc.). To address these issues, we improve the parallel modularization algorithm and discover its feasibility to confront all sorts of fault trees. Generally, K out of N gate is usually transformed into the combination of AND gates and OR gates, but that will significant increase the scale of the tree and consume more computation resources. As a solution, we treat the K out of N gate as a single module which could be encoded by BDD directly, and then the scale of entire fault tree could be controlled. Besides, we take the non-coherent fault tree and dynamic fault tree into account and find that these complicated logic gates can be regarded as modules too. We can draw the conclusion that our algorithm can be applied to all sorts of fault trees. Moreover, a detailed improvement of the algorithm is that we only start the algorithm from the bottom events with more than one outgoing edges, and that means we need not to traverse all nodes of the large fault tree. It is meaningful to save the computation resources. In the experiment section, we compare computation time of the improving algorithm with our previous works. And illustrates that the superiority of the improving algorithm through some graphs in various aspects.
AB - Modularization is a significant way to ease the challenge of evaluating large-scale fault trees known as a NP-hard problem, especially for BDD algorithm. In our previous work, we proposed an effective parallel modularization algorithm for large-scale coherent fault trees which only include gates with AND logic and OR logic. But in real engineering scenarios, fault trees usually consist of many complex static logic gates (i.e. K out of N gate, NOT gate, etc.) and dynamic logic gates (i.e. sequence gate, functional dependency gate, etc.). To address these issues, we improve the parallel modularization algorithm and discover its feasibility to confront all sorts of fault trees. Generally, K out of N gate is usually transformed into the combination of AND gates and OR gates, but that will significant increase the scale of the tree and consume more computation resources. As a solution, we treat the K out of N gate as a single module which could be encoded by BDD directly, and then the scale of entire fault tree could be controlled. Besides, we take the non-coherent fault tree and dynamic fault tree into account and find that these complicated logic gates can be regarded as modules too. We can draw the conclusion that our algorithm can be applied to all sorts of fault trees. Moreover, a detailed improvement of the algorithm is that we only start the algorithm from the bottom events with more than one outgoing edges, and that means we need not to traverse all nodes of the large fault tree. It is meaningful to save the computation resources. In the experiment section, we compare computation time of the improving algorithm with our previous works. And illustrates that the superiority of the improving algorithm through some graphs in various aspects.
KW - directed acyclic graph
KW - fault tree
KW - modularization
KW - parallel algorithm
UR - https://www.scopus.com/pages/publications/84968912333
U2 - 10.1109/RAMS.2016.7447964
DO - 10.1109/RAMS.2016.7447964
M3 - 会议稿件
AN - SCOPUS:84968912333
T3 - Proceedings - Annual Reliability and Maintainability Symposium
BT - Annual Reliability and Maintainability Symposium, RAMS 2016 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Annual Reliability and Maintainability Symposium, RAMS 2016
Y2 - 25 January 2016 through 28 January 2016
ER -