HyIMC: A 16 TOPS/W Hybrid Analog-Digital In-Memory Computing SoC with Model Compression and Recurrent Optimization for Deep Learning-Based Speech Enhancement

In-memory computing (IMC) presents a promising avenue for deep learning-based speech enhancement (DL-SE). However, the current state-of-the-art IMC architectures are hindered by their inability to simultaneously achieve high precision and energy efficiency, coupled with a lack of parallelism necessary for DL-SE’s distinctive temporal dependency. This paper introduces the HyIMC, which features: 1) an analog-digital hybrid IMC architecture that facilitates DL-SE algorithms; 2) a schedule controller designed to optimize recurrent dataflow in skip connections; and 3) non-key dimension shrinkage (NKDS), a model compression technique that retains superior accuracy while compressing DL-SE models. Our approach achieves 16 TOPS/W energy efficiency at system-level, implemented on a 40nm eFlash-based IMC SoC prototype. The HyIMC with NKDS compresses DL-SE model size by ∼83.3%, enhances the figure of merit by ∼1200%, and improves perceptual evaluation of speech quality score by ∼120%.