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High-speed data transmission system design and implementation based on FPGA

  • Bei Yan*
  • , Yuefeng Sun
  • *此作品的通讯作者
  • Beihang University

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

Aimed at the non-standard Flash memory composed of 8 K9KAG08U0M Flash chips of Samsung Company, the paper introduces a high-speed data transfer interface with FPGA (Field Programmable Gate Array) as the main controller. With the synchronous DMA (Direct Memory Access) mode of USB2.0, the system implements the management, reading and transmission of the data in the memory. The design of the system proves in practice that the effective transmission speed reaches 30MB/s and in just 15 minutes, all of the data in the 16.5G bytes non-standard memory can be downloaded to the hard disk of the computer.

源语言英语
主期刊名Proceedings - 2009 International Conference on Information Engineering and Computer Science, ICIECS 2009
DOI
出版状态已出版 - 2009
活动2009 International Conference on Information Engineering and Computer Science, ICIECS 2009 - Wuhan, 中国
期限: 19 12月 200920 12月 2009

出版系列

姓名Proceedings - 2009 International Conference on Information Engineering and Computer Science, ICIECS 2009

会议

会议2009 International Conference on Information Engineering and Computer Science, ICIECS 2009
国家/地区中国
Wuhan
时期19/12/0920/12/09

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