TY - JOUR
T1 - High-Frequency Low-Power Magnetic Full-Adder Based on Magnetic Tunnel Junction with Spin-Hall Assistance
AU - Deng, Erya
AU - Wang, Zhaohao
AU - Klein, Jacques Olivier
AU - Prenat, Guillaume
AU - Dieny, Bernard
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/11/1
Y1 - 2015/11/1
N2 - Perpendicular-anisotropy magnetic tunnel junction (MTJ) is one of the most promising candidates to build hybrid logic-in-memory architecture, because of its nonvolatility, infinite endurance, and 3-D integration with a CMOS technology. A novel magnetic full-adder (MFA) based on this architecture is proposed, with MTJs switched by spin-Hall-assisted spin-transfer torque (STT). Owing to the assistance of spin-Hall effect (SHE), MTJ switching time can significantly be reduced, and high operation frequency can be achieved. Moreover, the endurance of oxide barrier is largely enhanced as the requirement of lower write voltage. Using an industrial CMOS 28 nm design kit and a physics-based three-terminal spin-Hall-assisted STT-MTJ model, functionality and performance of the proposed MFA have been simulated and validated. A 1 ns STT current pulse assisted by 0.35 ns SHE current pulse is sufficient to switch the MTJ configuration. When compared with the previous MFAs based on STT-MTJ, the proposed MFA achieves 38% less operation time and 31% less power consumption to perform read and write operations.
AB - Perpendicular-anisotropy magnetic tunnel junction (MTJ) is one of the most promising candidates to build hybrid logic-in-memory architecture, because of its nonvolatility, infinite endurance, and 3-D integration with a CMOS technology. A novel magnetic full-adder (MFA) based on this architecture is proposed, with MTJs switched by spin-Hall-assisted spin-transfer torque (STT). Owing to the assistance of spin-Hall effect (SHE), MTJ switching time can significantly be reduced, and high operation frequency can be achieved. Moreover, the endurance of oxide barrier is largely enhanced as the requirement of lower write voltage. Using an industrial CMOS 28 nm design kit and a physics-based three-terminal spin-Hall-assisted STT-MTJ model, functionality and performance of the proposed MFA have been simulated and validated. A 1 ns STT current pulse assisted by 0.35 ns SHE current pulse is sufficient to switch the MTJ configuration. When compared with the previous MFAs based on STT-MTJ, the proposed MFA achieves 38% less operation time and 31% less power consumption to perform read and write operations.
KW - Hybrid logic-in-memory
KW - magnetic full-adder (MFA)
KW - magnetic tunnel junction (MTJ)
KW - spin-Hall effect (SHE)
KW - spin-transfer torque (STT)
UR - https://www.scopus.com/pages/publications/84946198995
U2 - 10.1109/TMAG.2015.2449554
DO - 10.1109/TMAG.2015.2449554
M3 - 文章
AN - SCOPUS:84946198995
SN - 0018-9464
VL - 51
JO - IEEE Transactions on Magnetics
JF - IEEE Transactions on Magnetics
IS - 11
M1 - 7132762
ER -