From APE to APE-100: From 1 to 100 gflops in lattice gauge theory simulations

N. Avico; P. Bacilieri; S. Cabasino; N. Cabibbo; L. A. Fernández; G. Fiorentini; A. Lai; M. P. Lombardo; E. Marinari; F. Marzano; P. Paolucci; G. Parisi; J. Pech; F. Rapuano; E. Remiddi; R. Sarno; G. Salina; A. Tarancón; G. M. Todesco; M. Torelli; R. Tripiccione; W. Tross

doi:10.1016/0010-4655(89)90229-4

From APE to APE-100: From 1 to 100 gflops in lattice gauge theory simulations

N. Avico^*
, P. Bacilieri
, S. Cabasino
, N. Cabibbo
, L. A. Fernández
, G. Fiorentini
, A. Lai
, M. P. Lombardo
, E. Marinari
, F. Marzano
, P. Paolucci
, G. Parisi
, J. Pech
, F. Rapuano
, E. Remiddi
, R. Sarno
, G. Salina
, A. Tarancón
, G. M. Todesco
, M. Torelli

R. Tripiccione, W. Tross

^*此作品的通讯作者

科研成果: 期刊稿件 › 文章 › 同行评审

9 引用（Scopus）

摘要

We briefly describe the APE processor, a parallel computer currently used in lattice gauge simulations. We also present in greater details the architecture and the implementation of APE-100, a fine grained SIMD processors for lattice gauge theory simulations, similar in structure to APE and designed to provide floating-point performance in the 100 Gflops range.

源语言	英语
页（从-至）	285-289
页数	5
期刊	Computer Physics Communications
卷	57
期	1-3
DOI	https://doi.org/10.1016/0010-4655(89)90229-4
出版状态	已出版 - 2 12月 1989
已对外发布	是

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Avico, N., Bacilieri, P., Cabasino, S., Cabibbo, N., Fernández, L. A., Fiorentini, G., Lai, A., Lombardo, M. P., Marinari, E., Marzano, F., Paolucci, P., Parisi, G., Pech, J., Rapuano, F., Remiddi, E., Sarno, R., Salina, G., Tarancón, A., Todesco, G. M., ... Tross, W. (1989). From APE to APE-100: From 1 to 100 gflops in lattice gauge theory simulations. Computer Physics Communications, 57(1-3), 285-289. https://doi.org/10.1016/0010-4655(89)90229-4

@article{f0c8c98d9b5a4818aed986ef996fb108,

title = "From APE to APE-100: From 1 to 100 gflops in lattice gauge theory simulations",

abstract = "We briefly describe the APE processor, a parallel computer currently used in lattice gauge simulations. We also present in greater details the architecture and the implementation of APE-100, a fine grained SIMD processors for lattice gauge theory simulations, similar in structure to APE and designed to provide floating-point performance in the 100 Gflops range.",

author = "N. Avico and P. Bacilieri and S. Cabasino and N. Cabibbo and Fern{\'a}ndez, \{L. A.\} and G. Fiorentini and A. Lai and Lombardo, \{M. P.\} and E. Marinari and F. Marzano and P. Paolucci and G. Parisi and J. Pech and F. Rapuano and E. Remiddi and R. Sarno and G. Salina and A. Taranc{\'o}n and Todesco, \{G. M.\} and M. Torelli and R. Tripiccione and W. Tross",

year = "1989",

month = dec,

day = "2",

doi = "10.1016/0010-4655(89)90229-4",

language = "英语",

volume = "57",

pages = "285--289",

journal = "Computer Physics Communications",

issn = "0010-4655",

publisher = "Elsevier B.V.",

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}

Avico, N, Bacilieri, P, Cabasino, S, Cabibbo, N, Fernández, LA, Fiorentini, G, Lai, A, Lombardo, MP, Marinari, E, Marzano, F, Paolucci, P, Parisi, G, Pech, J, Rapuano, F, Remiddi, E, Sarno, R, Salina, G, Tarancón, A, Todesco, GM, Torelli, M, Tripiccione, R & Tross, W 1989, 'From APE to APE-100: From 1 to 100 gflops in lattice gauge theory simulations', Computer Physics Communications, 卷 57, 号码 1-3, 页码 285-289. https://doi.org/10.1016/0010-4655(89)90229-4

TY - JOUR

T1 - From APE to APE-100

T2 - From 1 to 100 gflops in lattice gauge theory simulations

AU - Avico, N.

AU - Bacilieri, P.

AU - Cabasino, S.

AU - Cabibbo, N.

AU - Fernández, L. A.

AU - Fiorentini, G.

AU - Lai, A.

AU - Lombardo, M. P.

AU - Marinari, E.

AU - Marzano, F.

AU - Paolucci, P.

AU - Parisi, G.

AU - Pech, J.

AU - Rapuano, F.

AU - Remiddi, E.

AU - Sarno, R.

AU - Salina, G.

AU - Tarancón, A.

AU - Todesco, G. M.

AU - Torelli, M.

AU - Tripiccione, R.

AU - Tross, W.

PY - 1989/12/2

Y1 - 1989/12/2

N2 - We briefly describe the APE processor, a parallel computer currently used in lattice gauge simulations. We also present in greater details the architecture and the implementation of APE-100, a fine grained SIMD processors for lattice gauge theory simulations, similar in structure to APE and designed to provide floating-point performance in the 100 Gflops range.

AB - We briefly describe the APE processor, a parallel computer currently used in lattice gauge simulations. We also present in greater details the architecture and the implementation of APE-100, a fine grained SIMD processors for lattice gauge theory simulations, similar in structure to APE and designed to provide floating-point performance in the 100 Gflops range.

UR - https://www.scopus.com/pages/publications/0024933069

U2 - 10.1016/0010-4655(89)90229-4

DO - 10.1016/0010-4655(89)90229-4

M3 - 文章

AN - SCOPUS:0024933069

SN - 0010-4655

VL - 57

SP - 285

EP - 289

JO - Computer Physics Communications

JF - Computer Physics Communications

IS - 1-3

ER -

From APE to APE-100: From 1 to 100 gflops in lattice gauge theory simulations

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