FPGA design and implementation of high secure channel coding based AES

However applying encryption in physical layer reveals high levels of security, it can increase the system complexity and it can affect the communication reliability. This paper shows how to overcome these problems, where it doesn’t only show the design of combined Low Density Parity Check (LDPC) code and Customized Stream Advanced Encryption Standard (CSAES) to increase the security level, but it also introduces a practical implementation for it. The proposed algorithm is designed in order to optimally exploit the hardware resources, and FPGA parallelism to achieve high throughput and to save hardware size. The design method shows how channel coding can be exploited to increase the security and resist attacks without affecting the communication reliability. The proposed algorithm is implemented on (Cyclone-IV4CE115) to achieve variable throughputs. It achieves 604 Mbps and 10⁻⁶ BER at SNR = 3.25 dB, while it can achieve 2 Gbps for SNR greater than 6 dB. NIST tests are applied to check the ciphered output randomness, and also the resistance of the algorithm against some attacks is discussed.