FPGA-based hardware-efficient architecture for variable block-size motion estimation

To improve the hardware efficiency of the FPGA-based (field programmable gate array based) architecture for variable block-size motion estimation, a novel architecture was proposed, which was optimized in both area and speed. This architecture introduced RAM-based SAD (sum of absolute differences) accumulators, which had better performance than register-based combiner in both area and speed. To improve the speed of SADs' comparison and support partial difference eliminating algorithm, the architecture adopted a systolic comparing chain, which substituted for the bus-based comparator used in former designs. Based on Virtex-II family FPGA from Xilinx Inc., the proposed architecture consumed only 2261 slices, with the clock frequency as high as 164 MHz. It means that the architecture could process standard-definition format video with 16×16 search window in real-time. Compared with similar designs, the architecture could save the area by 77% and increase the speed by 218%.