Folivora: Ultralow-Power Microprocessor Design with Nano-Electromechanical Relay and Nanotube Memory

In the post-Moore era, CMOS technology scaling has encountered enormous design and fabrication challenges. 'Power Wall' limits the further increase of integration density. Emerging AI computing and data center deployments aggravate the power consumption problem further. In the pursuit of an efficient computing paradigm, nano-electromechanical (NEM) relay and nanotube random access memory (NRAM) technology have attracted enormous attention and have ultralow-power consumption compared with CMOS counterparts. NEM relay is a kind of device based on electronic and mechanical interaction switching, characterized by remarkably low power consumption. This article explores the application of NEM relay and NRAM technology to build a complex RISC processor, aiming to achieve much lower power without degrading performance. The controller and data path can be implemented with primitive logic gates made of NEM relays, and the on-chip cache can be implemented with NRAM. Experimental results show that the energy efficiency of the processor design based on NEM relay and NRAM can be improved by 88.2% and 78.9% compared with CMOS technology-based in-order and out-of-order microprocessors, respectively. Meanwhile, the performance can be improved by 42.9% and the instruction execution time can be reduced by more than 17.9%, which implies the potential of NEM relay and NRAM for emerging ultralow-power applications.