@inproceedings{65557467e184437c8a270674ecfa0e43,
title = "Field-Based 3D Capacitance Modeling for sub-45-nm On-Chip Interconnect",
abstract = "Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error in a traditional model fitting process. The new compact model accurately predicts the capacitance value, compared to the COMSOL simulations, for not only the nominal wire dimensions from the latest ITRS updates, but also a wide range of other back-end-of-the-line dimensions.",
keywords = "Capacitance modeling, Electric field, Fringe capacitance, Interconnect, Terminal capacitance",
author = "Aixi Zhang and Wei Zhao and Yun Ye and Jin He and Aixin Chen and Mansun Chan",
year = "2012",
language = "英语",
isbn = "9781466562752",
series = "Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012",
publisher = "Nano Science and Technology Institute",
pages = "804--808",
booktitle = "Nanotechnology 2012",
note = "Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012 ; Conference date: 18-06-2012 Through 21-06-2012",
}