TY - JOUR
T1 - Experimental verification of multidirectional multiscroll chaotic attractors
AU - Lü, Jinhu
AU - Yu, Simin
AU - Leung, Henry
AU - Chen, Guanrong
PY - 2006/1
Y1 - 2006/1
N2 - A systematic methodology for circuit design is proposed for experimental verification of multidirectional multiscroll chaotic attractors, including one-directional (1-D) n-scroll, 2-D n × m-grid scroll, and 3-D n × m × l-grid scroll chaotic attractors. Two typical cases are investigated in detail: the hysteresis and saturated multiscroll chaotic attractors. A simple blocking circuit diagram is designed for experimentally verifying 1-D 5 ∼ 11-scroll, 2-D 3 × 5 ∼ 11-grid scroll, and 3-D 3 × 3× 5 ∼ 11-grid scroll hysteresis chaotic attractors by manipulating the switchers. Moreover, a block circuitry is also designed for physically realizing 1-D 10, 12, 14-scroll, 2-D 10, 12, 14 × 10-grid scroll, and 3-D 10 × 10 × 10-grid scroll saturated chaotic attractors via switching. In addition, one can easily realize chaotic attractors with a desired odd number of scrolls by slightly modifying the corresponding voltage saturated function series of the circuit, to produce for instance a 1-D 13-scroll saturated chaotic attractor. This is the first time in the literature to report an experimental verification of a 1-D 14-scroll, a 2-D 14 × 10-grid scroll and a 3-D 10 × 10 × 10-grid (totally 1000) scroll chaotic attractors. Only the 3-D case is reported in detail for simplicity of presentation. It is well known that hardware implementation of 1-D n-scroll with n ≥10, 2-D n × m-grid scroll with n,m ≥ 10 and 3-D n × m × l-grid scroll with n, m, l ≥ 10 chaotic attractors is very difficult technically, signifying the novelty and significance of the achievements reported in this paper. Finally, this circuit design approach provides some principles and guidelines for hardware implementation of chaotic attractors with a multidirectional orientation and with a large number of scrolls, useful for future circuitry design and engineering applications.
AB - A systematic methodology for circuit design is proposed for experimental verification of multidirectional multiscroll chaotic attractors, including one-directional (1-D) n-scroll, 2-D n × m-grid scroll, and 3-D n × m × l-grid scroll chaotic attractors. Two typical cases are investigated in detail: the hysteresis and saturated multiscroll chaotic attractors. A simple blocking circuit diagram is designed for experimentally verifying 1-D 5 ∼ 11-scroll, 2-D 3 × 5 ∼ 11-grid scroll, and 3-D 3 × 3× 5 ∼ 11-grid scroll hysteresis chaotic attractors by manipulating the switchers. Moreover, a block circuitry is also designed for physically realizing 1-D 10, 12, 14-scroll, 2-D 10, 12, 14 × 10-grid scroll, and 3-D 10 × 10 × 10-grid scroll saturated chaotic attractors via switching. In addition, one can easily realize chaotic attractors with a desired odd number of scrolls by slightly modifying the corresponding voltage saturated function series of the circuit, to produce for instance a 1-D 13-scroll saturated chaotic attractor. This is the first time in the literature to report an experimental verification of a 1-D 14-scroll, a 2-D 14 × 10-grid scroll and a 3-D 10 × 10 × 10-grid (totally 1000) scroll chaotic attractors. Only the 3-D case is reported in detail for simplicity of presentation. It is well known that hardware implementation of 1-D n-scroll with n ≥10, 2-D n × m-grid scroll with n,m ≥ 10 and 3-D n × m × l-grid scroll with n, m, l ≥ 10 chaotic attractors is very difficult technically, signifying the novelty and significance of the achievements reported in this paper. Finally, this circuit design approach provides some principles and guidelines for hardware implementation of chaotic attractors with a multidirectional orientation and with a large number of scrolls, useful for future circuitry design and engineering applications.
KW - Circuit implementation
KW - Hysteresis series
KW - Multidirectional chaotic attractor
KW - Multiscroll chaotic attractor
KW - Saturated series
UR - https://www.scopus.com/pages/publications/31344435935
U2 - 10.1109/TCSI.2005.854412
DO - 10.1109/TCSI.2005.854412
M3 - 文章
AN - SCOPUS:31344435935
SN - 1549-8328
VL - 53
SP - 149
EP - 165
JO - IEEE Transactions on Circuits and Systems
JF - IEEE Transactions on Circuits and Systems
IS - 1
ER -