TY - GEN
T1 - Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM
AU - Zhang, He
AU - Kang, Wang
AU - Pang, Tingting
AU - Lv, Weifeng
AU - Zhang, Youguang
AU - Zhao, Weisheng
N1 - Publisher Copyright:
� 2016 ACM.
PY - 2016/9/14
Y1 - 2016/9/14
N2 - Spin transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation nonvolatile memory. However, because of the increased process variations and reduced critical switching current of the magnetic tunnel junction (MTJ), the readability has become a new obstacle for STT-MRAM in scaled technology nodes. Thermal fluctuations further aggravates this phenomenon. There are multifarious sensing schemes and circuits have been proposed recently to bate this problem. However the technical advancement is incremental and the performance improvement is limited as technology continuously scales. In this paper, we propose a novel sensing circuit to achieve constant-current sensing, named triple steady states sensing circuit (TSSSC), which directly compares the P/AP state with the P/AP state of the memory cell to improve the sensing margin (SM). Using a physics-based MTJ model and the STMicroelectronics process design-kit, Monte-Carlo simulations were carried out at 40 nm technology node. The results validate the effectiveness of the proposed sensing scheme.
AB - Spin transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation nonvolatile memory. However, because of the increased process variations and reduced critical switching current of the magnetic tunnel junction (MTJ), the readability has become a new obstacle for STT-MRAM in scaled technology nodes. Thermal fluctuations further aggravates this phenomenon. There are multifarious sensing schemes and circuits have been proposed recently to bate this problem. However the technical advancement is incremental and the performance improvement is limited as technology continuously scales. In this paper, we propose a novel sensing circuit to achieve constant-current sensing, named triple steady states sensing circuit (TSSSC), which directly compares the P/AP state with the P/AP state of the memory cell to improve the sensing margin (SM). Using a physics-based MTJ model and the STMicroelectronics process design-kit, Monte-Carlo simulations were carried out at 40 nm technology node. The results validate the effectiveness of the proposed sensing scheme.
KW - Dual reference sensing
KW - STT-MRAM
KW - read reliability
KW - sensing margin (SM)
UR - https://www.scopus.com/pages/publications/84992036791
U2 - 10.1145/2950067.2950102
DO - 10.1145/2950067.2950102
M3 - 会议稿件
AN - SCOPUS:84992036791
T3 - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
SP - 1
EP - 6
BT - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
PB - Presses Polytechniques Et Universitaires Romandes
T2 - 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Y2 - 18 July 2016 through 20 July 2016
ER -