Design of simulation system of the synthesis loop for testing the closing capacity of high voltage breaker

To conduct small-capacity synthesis tests in laboratory, to save the cost of synthesis tests for debugging synchronous control system, and to make the debugging of synchronous control system convenient, we developed a set of simulation system for synthesis loop tests. Firstly, on the basis of analyzing Wiel test and high-voltage closing test, we calculated the component parameters for the main circuit of the simulation system. Secondly, according to the working characteristics of synthesis tests, we designed a control system of the simulation system. The simulation system uses SCM for time sequence control and meets the requirements of its design. According to the cooperation tests with the synchronous control system, it is obtained that the error of the actual trigger time is smaller than 50μs, and the error of the pro-long arc circuit is smaller than 40 μs, which ensures the equivalence of synthetic test and proves the feasibility of the proposed simulation system.