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Design of embedded MRAM macros for memory-in-logic applications

  • Sumanta Chaudhuri*
  • , Weisheng Zhao
  • , Jacques Olivier Klein
  • , Claude Chappert
  • , Pascale Mazoyer
  • *此作品的通讯作者
  • CNRS
  • Université Paris-Saclay
  • STMicroelectronics

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

In this article we present a design method for integrating non-volatile MRAM memory cells into standard CMOS design. The emphasis is on standard cell based flow for general purpose logic and automatic generation or MRAM macros suitable for the applications. We present a design space exploration for this purpose and transient simulation results of the hybrid MTJ/CMOS designs. We continue the article with examples of automatic macro generation, integration layout and a prototype in 130nm CMOS which is designed to test a large subset of this design space. In conclusion we show that a high 3D integration density with reasonable speed can be achieved with automatic flow by sharing the reading/writing circuitry among a number of MTJs.

源语言英语
主期刊名GLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
155-158
页数4
DOI
出版状态已出版 - 2010
已对外发布
活动20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, 美国
期限: 16 5月 201018 5月 2010

出版系列

姓名Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

会议

会议20th Great Lakes Symposium on VLSI, GLSVLSI 2010
国家/地区美国
Providence, RI
时期16/05/1018/05/10

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