TY - GEN
T1 - Design methods of multi-DSP parallel processing system
AU - Wei, Wu
AU - Jun, Wang
AU - Wei, Li
AU - Wenhao, Zhang
PY - 2009
Y1 - 2009
N2 - In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.
AB - In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.
UR - https://www.scopus.com/pages/publications/70449115204
U2 - 10.1109/CSIE.2009.40
DO - 10.1109/CSIE.2009.40
M3 - 会议稿件
AN - SCOPUS:70449115204
SN - 9780769535074
T3 - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
SP - 458
EP - 464
BT - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
T2 - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Y2 - 31 March 2009 through 2 April 2009
ER -