Design considerations and strategies for high-reliable STT-MRAM

Benefiting from Spin Transfer Torque (STT) switching approach, second generation of Magnetic RAM (MRAM) promises low power, great miniaturization prospective (<22 nm) and easy integration with CMOS process. It becomes actually a strong non-volatile memory candidate for both embedded and standalone applications. However STT-MRAM suffers from important reliability issues compared with the conventional one based on magnetic field switching, for example, a read-current could write erroneously the stored data, the low Resistance Area (RA) value drives high sensing error rate. This paper presents the considerations and strategies from design point of view for the reliability enhancement. Mixed transient and statistical simulations have been performed by using a STT-MRAM compact model and CMOS 65 nm design kit.