Design and implementation of scalable throughput fast convergence LDPC decoder

it is known that the more reliable LDPC code is the longer code, and it is also known that LDPC decoders with flooded architecture which allow parallel processing can achieve high throughputs. But, just architectures become very complex and require more hardware resources when the code length is large and random, so achieving a high error correction rate on short code lengths is considered a challenge. In this letter, an FPGA design and implementation of a scalable LDPC decoder for short code length are represented. The proposed LDPC decoder is based on the integration between Scaled MSA (SMS) with a Weighted Bit Flipping (WBF) algorithm to allow fast convergence and enhance the error rate, while high throughput is obtained from using flooded scheduling strategy. The results show that the new method can achieve BER reaches to 10^-6 and FER reaches to 10^-4 at 2.5 dB SNR over BAWGC using BPSK as a modulation scheme. In this letter also, the architecture of this algorithm is exploited to create a scalable design to achieve variable throughputs reaches to multi Gbps versus variable performances. A new scaling method that allows a 76% reduction, and new efficient design for WBF, are introduced.