Design and implementation of HDLC procedures based on FPGA

Wang Jun; Zhang Wenhao; Zhang Yuxi; Wu Wei; Chang Weiguang

doi:10.1109/ICASID.2009.5276893

Design and implementation of HDLC procedures based on FPGA

Wang Jun^*
, Zhang Wenhao
, Zhang Yuxi
, Wu Wei
, Chang Weiguang

^*此作品的通讯作者

电子信息工程学院

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

3 引用（Scopus）

摘要

High-level Data Link Control (HDLC) procedure is one of the most important protocols in digital communications. This paper analyzes the methods of HDLC procedure implementation commonly used nowadays, and points out their defects. We propose a new hardware implementation of HDLC procedure based on Field Programmable Gates Array (FPGA), and especially illustrate how to generate Frame Check Sequence (FCS) of HDLC - Cycle Redundancy Check (CRC) in FPGA. We verified the methods above by downloading the HDLC modules designed in VHDL (VHSIC Hardware Description Language) into FPGA, which shows the feasibility of the methods. The programming of modules is simple, easy to modify, and superior in practical application.

源语言	英语
主期刊名	2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009
DOI	https://doi.org/10.1109/ICASID.2009.5276893
出版状态	已出版 - 2009
活动	2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009 - Hong Kong, 中国期限: 20 8月 2009 → 22 8月 2009

出版系列

姓名	2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009

会议

会议	2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009
国家/地区	中国
市	Hong Kong
时期	20/08/09 → 22/08/09

访问文件

10.1109/ICASID.2009.5276893

其它文件与链接

链接到 Scopus 的出版物

引用此

Jun, W., Wenhao, Z., Yuxi, Z., Wei, W., & Weiguang, C. (2009). Design and implementation of HDLC procedures based on FPGA. 在 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009 文章 5276893 (2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009). https://doi.org/10.1109/ICASID.2009.5276893

@inproceedings{fba9a33e8dfe4acc87400377230a9e9c,

title = "Design and implementation of HDLC procedures based on FPGA",

abstract = "High-level Data Link Control (HDLC) procedure is one of the most important protocols in digital communications. This paper analyzes the methods of HDLC procedure implementation commonly used nowadays, and points out their defects. We propose a new hardware implementation of HDLC procedure based on Field Programmable Gates Array (FPGA), and especially illustrate how to generate Frame Check Sequence (FCS) of HDLC - Cycle Redundancy Check (CRC) in FPGA. We verified the methods above by downloading the HDLC modules designed in VHDL (VHSIC Hardware Description Language) into FPGA, which shows the feasibility of the methods. The programming of modules is simple, easy to modify, and superior in practical application.",

keywords = "FCS generation, CRC, FPGA, Finite state machine (FSM), HDLC procedures, Linear feedback shift register (LFSR)",

author = "Wang Jun and Zhang Wenhao and Zhang Yuxi and Wu Wei and Chang Weiguang",

year = "2009",

doi = "10.1109/ICASID.2009.5276893",

language = "英语",

isbn = "9781424438839",

series = "2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009",

booktitle = "2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009",

note = "2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009 ; Conference date: 20-08-2009 Through 22-08-2009",

}

Jun, W, Wenhao, Z, Yuxi, Z, Wei, W & Weiguang, C 2009, Design and implementation of HDLC procedures based on FPGA. 在 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009., 5276893, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009, Hong Kong, 中国, 20/08/09. https://doi.org/10.1109/ICASID.2009.5276893

Design and implementation of HDLC procedures based on FPGA. / Jun, Wang; Wenhao, Zhang; Yuxi, Zhang 等.
2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009. 2009. 5276893 (2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - Design and implementation of HDLC procedures based on FPGA

AU - Jun, Wang

AU - Wenhao, Zhang

AU - Yuxi, Zhang

AU - Wei, Wu

AU - Weiguang, Chang

PY - 2009

Y1 - 2009

N2 - High-level Data Link Control (HDLC) procedure is one of the most important protocols in digital communications. This paper analyzes the methods of HDLC procedure implementation commonly used nowadays, and points out their defects. We propose a new hardware implementation of HDLC procedure based on Field Programmable Gates Array (FPGA), and especially illustrate how to generate Frame Check Sequence (FCS) of HDLC - Cycle Redundancy Check (CRC) in FPGA. We verified the methods above by downloading the HDLC modules designed in VHDL (VHSIC Hardware Description Language) into FPGA, which shows the feasibility of the methods. The programming of modules is simple, easy to modify, and superior in practical application.

AB - High-level Data Link Control (HDLC) procedure is one of the most important protocols in digital communications. This paper analyzes the methods of HDLC procedure implementation commonly used nowadays, and points out their defects. We propose a new hardware implementation of HDLC procedure based on Field Programmable Gates Array (FPGA), and especially illustrate how to generate Frame Check Sequence (FCS) of HDLC - Cycle Redundancy Check (CRC) in FPGA. We verified the methods above by downloading the HDLC modules designed in VHDL (VHSIC Hardware Description Language) into FPGA, which shows the feasibility of the methods. The programming of modules is simple, easy to modify, and superior in practical application.

KW - FCS generation, CRC

KW - FPGA

KW - Finite state machine (FSM)

KW - HDLC procedures

KW - Linear feedback shift register (LFSR)

UR - https://www.scopus.com/pages/publications/72549110082

U2 - 10.1109/ICASID.2009.5276893

DO - 10.1109/ICASID.2009.5276893

M3 - 会议稿件

AN - SCOPUS:72549110082

SN - 9781424438839

T3 - 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009

BT - 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009

T2 - 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009

Y2 - 20 August 2009 through 22 August 2009

ER -

Jun W, Wenhao Z, Yuxi Z, Wei W, Weiguang C. Design and implementation of HDLC procedures based on FPGA. 在 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009. 2009. 5276893. (2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, ASID 2009). doi: 10.1109/ICASID.2009.5276893

Design and implementation of HDLC procedures based on FPGA

摘要

出版系列

会议

访问文件

其它文件与链接

指纹

引用此