TY - GEN
T1 - Design and High-Fidelity Verification of an Energy-Efficient NAND-Like SAS-MRAM for ReLU-Activated Feature Caching in CNN CIM
AU - Jiang, Xinpeng
AU - Wang, Chenyi
AU - Xu, Xiaoyang
AU - Sun, Sifan
AU - Wang, Zhaohao
AU - Zhang, He
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Magnetic random-access memory (MRAM) is an emerging non-volatile memory technology distinguished by its radiation hardness, high endurance, and CMOS process compatibility, positioning it as a promising candidate to replace static random-access memory (SRAM). However, mainstream MRAM devices exhibit low cache efficiency in digital computing-in-memory (CIM) architectures due to the inherent incompatibility between their writing mechanism and the ReLU output data structure. This paper proposes a NAND-Like SAS-MRAM (NLSAS-MRAM), which shows extremely high efficiency when writing zero-dominated data, and is therefore highly suitable for caching ReLU outputs. To rigorously verify this advantage, we developed a high-fidelity co-simulation flow. Simulation results show that the proposed NLSASMRAM achieves a writing power consumption of only 35% that of STT-MRAM and 63% of SOT-MRAM. Furthermore, it delivers a 52.6× improvement in cache potential FOM over STT-MRAM and a 2.6× improvement over SOT-MRAM.
AB - Magnetic random-access memory (MRAM) is an emerging non-volatile memory technology distinguished by its radiation hardness, high endurance, and CMOS process compatibility, positioning it as a promising candidate to replace static random-access memory (SRAM). However, mainstream MRAM devices exhibit low cache efficiency in digital computing-in-memory (CIM) architectures due to the inherent incompatibility between their writing mechanism and the ReLU output data structure. This paper proposes a NAND-Like SAS-MRAM (NLSAS-MRAM), which shows extremely high efficiency when writing zero-dominated data, and is therefore highly suitable for caching ReLU outputs. To rigorously verify this advantage, we developed a high-fidelity co-simulation flow. Simulation results show that the proposed NLSASMRAM achieves a writing power consumption of only 35% that of STT-MRAM and 63% of SOT-MRAM. Furthermore, it delivers a 52.6× improvement in cache potential FOM over STT-MRAM and a 2.6× improvement over SOT-MRAM.
KW - CNN
KW - NLSAS-MRAM
KW - ReLU activation cache
KW - high-fidelity verification
UR - https://www.scopus.com/pages/publications/105034655538
U2 - 10.1109/ICTA68203.2025.11329746
DO - 10.1109/ICTA68203.2025.11329746
M3 - 会议稿件
AN - SCOPUS:105034655538
T3 - 2025 IEEE 8th International Conference on Integrated Circuits, Technologies and Applications, ICTA 2025
SP - 133
EP - 134
BT - 2025 IEEE 8th International Conference on Integrated Circuits, Technologies and Applications, ICTA 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE 8th International Conference on Integrated Circuits, Technologies, and Applications, ICTA2025
Y2 - 22 October 2025 through 24 October 2025
ER -