TY - GEN
T1 - Demonstration of a NAND-Like SOT-MRAM Multi-Level Cell with Two Operational Modes
AU - Wang, Chenyi
AU - Yan, Zhengjie
AU - Wang, Min
AU - Wang, Zhaohao
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Multi-level cell (MLC) schemes have demonstrated effectiveness in scenarios such as neural network acceleration and multitask optimization. Leveraging several advantages, particularly its compatibility with complementary metal oxide semiconductor (CMOS) processes, the MLC scheme of MRAM has been widely researched. In this study, we propose an MLC-MRAM architecture based on spin-orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA) within a NAND-like structure, featuring two operational modes. One mode involves a one-step writing operation, enabling deterministic writing of four data states. It effectively addresses the previous annealing challenge associated with the MLC device and achieves reliable switching within a single step. The other mode combines SOT and VCMA effects in the two-step operation which facilitates multi-level storage. The experimental results confirm the existence of multiple resistance states, characterized by the minimal variation (a standard deviation of less than 6%). Our work verifies that the NAND-like SOT-MRAM MLC based on canted devices with in-plane magnetic anisotropy, achieves multi-level storage while satisfying the fundamental requirements for in-memory computing.
AB - Multi-level cell (MLC) schemes have demonstrated effectiveness in scenarios such as neural network acceleration and multitask optimization. Leveraging several advantages, particularly its compatibility with complementary metal oxide semiconductor (CMOS) processes, the MLC scheme of MRAM has been widely researched. In this study, we propose an MLC-MRAM architecture based on spin-orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA) within a NAND-like structure, featuring two operational modes. One mode involves a one-step writing operation, enabling deterministic writing of four data states. It effectively addresses the previous annealing challenge associated with the MLC device and achieves reliable switching within a single step. The other mode combines SOT and VCMA effects in the two-step operation which facilitates multi-level storage. The experimental results confirm the existence of multiple resistance states, characterized by the minimal variation (a standard deviation of less than 6%). Our work verifies that the NAND-like SOT-MRAM MLC based on canted devices with in-plane magnetic anisotropy, achieves multi-level storage while satisfying the fundamental requirements for in-memory computing.
UR - https://www.scopus.com/pages/publications/85203172832
U2 - 10.1109/NANO61778.2024.10628619
DO - 10.1109/NANO61778.2024.10628619
M3 - 会议稿件
AN - SCOPUS:85203172832
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 317
EP - 321
BT - 2024 IEEE 24th International Conference on Nanotechnology, NANO 2024
PB - IEEE Computer Society
T2 - 24th IEEE International Conference on Nanotechnology, NANO 2024
Y2 - 8 July 2024 through 11 July 2024
ER -