Complementary spintronic logic with spin hall effect driven magnetic tunnel junction

As the CMOS technology scales down, the leakage power becomes a critical barrier for high-performance processors. In addition, the separated processor and storage units in the classic Von-Neumann architecture limit the development of advanced computer design. Spintronics is an emerging platform for nonvolatile memory and logic circuit designs [1-2]. The nonvolatility of spintronics can reduce greatly the leakage power and the logic-in-memory feature enables to integrate both the memory and logic circuits within one chip, providing an opportunity to explore advanced computer architectures beyond classical Von-Neumann architecture. Recently, the spintronic memories, e.g., MRAM, have been commercialized in market [3]. However, the spintronic logics are facing lots of problems, e.g., the lack of a unified standard design methodology to implement the full Boolean logic functions. Although a number of proposals have been proposed, they do have a long step before practical commercialization. Here, we present a new approach, named complementary spintronic logic (CSL), which utilizes spin hall effect (SHE) driven magnetic tunnel junction (MTJ), to form CMOS-like logic design paradigm. Full Boolean logic functions can be performed using this unified standard design paradigm. By exploiting the SHE for independent writing and reading paths of the MTJ, it provides a variety of merits, such as high reliability, low power and high speed etc. Furthermore, this logic family can permit direct cascading and be integrated within the cross-point architecture to offer high-density implementation. This abstract highlights the capability of the proposed CSL family to perform full Boolean logic functions.