Cell array reconfigurable architecture for high-efficiency AES system

This paper present the issue of standard security algorithms with reconfigurable cell array architecture. The reconfigurable Advanced Encryption Standard (AES) architecture is proposed for high performance information security applications. The reconfiguration architecture based on cell array processing elements is connected to each other through the interconnect routing and the switchbox. AES operations are performed on a two-dimensional array using four rows and four columns for the encryption with 128-bit Key length. The Key expansion unit is set the flexible architecture with 128-, 196- and 256-bit cipher Key length. The reconfigurable Key generator further increases the AES hardware flexibility. The operation of SubBytes and XOR is implemented with internal cell of array, but ShiftRow and MixColumns must depend on co-ordination between cells of array. Sixteen free cells of array are connected using the switchbox to operate the encryption of AES algorithm. The on-line fault detection based on parity code is designed to check fault cell. The cell array AES architecture is simulated with Verilog HDL. The prototype system of reconfigurable cell array AES is verified using a field programmable gate array (FPGA). The experiment results show that the proposed method achieves a high-efficiency, low-hardware overhead and high reliability for the information security.