Based on 1 or 0 BNN Accelerator with Array Architecture

Zhangkong Xian; Hongge Li; Yuliang Li

doi:10.1109/ICTA48799.2019.9012873

Based on 1 or 0 BNN Accelerator with Array Architecture

Zhangkong Xian
, Hongge Li
, Yuliang Li

电子信息工程学院

Beihang University

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

In this paper, we introduce a binary convolutional neural network accelerator which using a new binarization method. We propose the weights and the activations to either 1 or 0 instead of +1 or-1, which makes the convolution process simplified and more suitable for hardware implementation. To decrease the data access from off-chip memory, we propose a novel method of the data reuse, which can reduce 58.8% data access. Our accelerator is implemented on the VC709 Evaluation Kit. Experimental results show that the proposed accelerator achieves a throughput of 3378 GOPS and 1624 GOPS/W energy efficiency.

源语言	英语
主期刊名	2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings
出版商	Institute of Electrical and Electronics Engineers Inc.
页	79-80
页数	2
ISBN（电子版）	9781728151670
DOI	https://doi.org/10.1109/ICTA48799.2019.9012873
出版状态	已出版 - 11月 2019
活动	2nd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Chengdu, 中国期限: 13 11月 2019 → 15 11月 2019

出版系列

姓名	2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings

会议

会议	2nd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019
国家/地区	中国
市	Chengdu
时期	13/11/19 → 15/11/19

联合国可持续发展目标

此成果有助于实现下列可持续发展目标：

可持续发展目标 7 经济适用的清洁能源

访问文件

10.1109/ICTA48799.2019.9012873

其它文件与链接

链接到 Scopus 的出版物

引用此

Xian, Z., Li, H., & Li, Y. (2019). Based on 1 or 0 BNN Accelerator with Array Architecture. 在 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings (页码 79-80). 文章 9012873 (2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICTA48799.2019.9012873

Xian, Zhangkong ; Li, Hongge ; Li, Yuliang. / Based on 1 or 0 BNN Accelerator with Array Architecture. 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 页码 79-80 (2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings).

@inproceedings{9c0a50767f0f400195b1f117f42fc5d6,

title = "Based on 1 or 0 BNN Accelerator with Array Architecture",

abstract = "In this paper, we introduce a binary convolutional neural network accelerator which using a new binarization method. We propose the weights and the activations to either 1 or 0 instead of +1 or-1, which makes the convolution process simplified and more suitable for hardware implementation. To decrease the data access from off-chip memory, we propose a novel method of the data reuse, which can reduce 58.8\% data access. Our accelerator is implemented on the VC709 Evaluation Kit. Experimental results show that the proposed accelerator achieves a throughput of 3378 GOPS and 1624 GOPS/W energy efficiency.",

keywords = "BNN, data reuse, energy efficiency, throughput",

author = "Zhangkong Xian and Hongge Li and Yuliang Li",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2nd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 ; Conference date: 13-11-2019 Through 15-11-2019",

year = "2019",

month = nov,

doi = "10.1109/ICTA48799.2019.9012873",

language = "英语",

series = "2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "79--80",

booktitle = "2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings",

address = "美国",

}

Xian, Z, Li, H & Li, Y 2019, Based on 1 or 0 BNN Accelerator with Array Architecture. 在 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings., 9012873, 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 页码 79-80, 2nd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019, Chengdu, 中国, 13/11/19. https://doi.org/10.1109/ICTA48799.2019.9012873

Based on 1 or 0 BNN Accelerator with Array Architecture. / Xian, Zhangkong; Li, Hongge; Li, Yuliang.
2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 页码 79-80 9012873 (2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - Based on 1 or 0 BNN Accelerator with Array Architecture

AU - Xian, Zhangkong

AU - Li, Hongge

AU - Li, Yuliang

PY - 2019/11

Y1 - 2019/11

N2 - In this paper, we introduce a binary convolutional neural network accelerator which using a new binarization method. We propose the weights and the activations to either 1 or 0 instead of +1 or-1, which makes the convolution process simplified and more suitable for hardware implementation. To decrease the data access from off-chip memory, we propose a novel method of the data reuse, which can reduce 58.8% data access. Our accelerator is implemented on the VC709 Evaluation Kit. Experimental results show that the proposed accelerator achieves a throughput of 3378 GOPS and 1624 GOPS/W energy efficiency.

AB - In this paper, we introduce a binary convolutional neural network accelerator which using a new binarization method. We propose the weights and the activations to either 1 or 0 instead of +1 or-1, which makes the convolution process simplified and more suitable for hardware implementation. To decrease the data access from off-chip memory, we propose a novel method of the data reuse, which can reduce 58.8% data access. Our accelerator is implemented on the VC709 Evaluation Kit. Experimental results show that the proposed accelerator achieves a throughput of 3378 GOPS and 1624 GOPS/W energy efficiency.

KW - BNN

KW - data reuse

KW - energy efficiency

KW - throughput

UR - https://www.scopus.com/pages/publications/85081985774

U2 - 10.1109/ICTA48799.2019.9012873

DO - 10.1109/ICTA48799.2019.9012873

M3 - 会议稿件

AN - SCOPUS:85081985774

T3 - 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings

SP - 79

EP - 80

BT - 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019

Y2 - 13 November 2019 through 15 November 2019

ER -

Xian Z, Li H, Li Y. Based on 1 or 0 BNN Accelerator with Array Architecture. 在 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 页码 79-80. 9012873. (2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings). doi: 10.1109/ICTA48799.2019.9012873

Based on 1 or 0 BNN Accelerator with Array Architecture

摘要

出版系列

会议

联合国可持续发展目标

访问文件

其它文件与链接

指纹

引用此